Modeling and Verifying of 3D Network-on-Chip Benchmarks for the RatatoskrM3D Simulator
As part of this work, several benchmarks for 3D network-on-chips (NoC) shall be further developed. The basis is the RatatoskrM3D project developed at the chair, which includes a NoC simulator. Furthermore, the simulation results shall be compared and verified with other simulators.

• Research Project or Bachelor/Master Thesis
• Supervisor: M.Sc Max Tzschoppe

Embedded Vision Algorithms
Embedded vision algorithm development and FPGA-based hardware implementation. Required Knowledge: C, high-level synthesis, image processing, FPGA programming helpful.

• Bachelor/Master
• Supervisor: Dr.-Ing. Gerald Krell

A Linear Programming Model for Operator Mapping on FPGAs
In this thesis, a linear program should be developed and implemented to map operator graphs onto FPGAs. The focus lies on the mathematical modelling of the problem. The thesis topic is aimed at master or motivated bachelor students.

• Bachelor/Master
• Supervisor: Dr.-Ing. Martin Wilhelm

Latency Measures in Network-on-Chips
In this work, various measures for the quality of a Network-on-Chip should be evaluated and compared. For this, meaningful examples as well as alternative measures should be derived using a NoC simulator. The topic is aimed at master or motivated bachelor students.

• Bachelor/Master
• Supervisor: Dr.-Ing. Martin Wilhelm