Chair Hardware-Oriented Technical Computer Science

Topics

Modeling and Verifying of 3D Network-on-Chip Benchmarks for the RatatoskrM3D Simulator
As part of this work, several benchmarks for 3D network-on-chips (NoC) shall be further developed. The basis is the RatatoskrM3D project developed at the chair, which includes a NoC simulator. Furthermore, the simulation results shall be compared and verified with other simulators.

Hardware implementation of virtual memory for FPGAs for use in database systems with heterogeneous hardware
In this thesis the use of virtual memory for FPGAs is investigated. An existing accelerator system is extended in different techniques (hardware design with VHDL, system programming in C) to reduce the management effort for the host server and to use the physical memory available on the FPGA accelerator card more efficiently.

Embedded Vision Algorithms
Embedded vision algorithm development and FPGA-based hardware implementation. Required Knowledge: C, high-level synthesis, image processing, FPGA programming helpful.

 Approximate Computing in CT image reconstruction

In the context of this thesis, the use of Approximate Computing on Heterogeneous Architectures is investigated. Real-time Computed Tomography reconstruction algorithms are the target application. The student can select an accelerator architecture, such as GPUs, Tensor Cores, FPGAs, for the enhancement of these algorithms.

Design-Space Exploration for configurable Network-on-Chip in Mixed-Criticality Systems
In the context of this thesis, configurable Network-on-Chip are investigated. The student contribute in the definition of a framework that generate the Hardware Design of an input application and workload from Mixed-Criticality Systems. The aim is to analyse the behavioral of the communication in the running system, during the mission time.

CT image reconstruction on MPSoC
In the context of this thesis, the use of MPSoC for Computed Thomography image reconstruction is investigated. Real-time Computed Tomography reconstruction algorithms are the target application. The student can select an accelerator architecture iside the MPSoC, such as GPUs, DSPs, AI Engines, FPGAs, for the enhancement of these algorithms. Multiple architecture can be choosen in a Hardware/Software Codesign solution.

A Linear Programming Model for Operator Mapping on FPGAs
In this thesis, a linear program should be developed and implemented to map operator graphs onto FPGAs. The focus lies on the mathematical modelling of the problem. The thesis topic is aimed at master or motivated bachelor students.

Latency Measures in Network-on-Chips
In this work, various measures for the quality of a Network-on-Chip should be evaluated and compared. For this, meaningful examples as well as alternative measures should be derived using a NoC simulator. The topic is aimed at master or motivated bachelor students.

Last Modification: 29.08.2024 - Contact Person: Webmaster